// PIC18 in C - Versione 0.80 - Luglio 2015 // Copyright (c) 2015, Vincenzo Villa // Creative Commons | Attribuzione - Condividi allo stesso modo 4.0 Internazionale (CC BY-SA 4.0) // Creative Commons | Attribution-Share Alike 4.0 Unported // https://www.vincenzov.net/tutorial/PIC18/SPI-interrupt-Timer2.htm // PIC18F25K20 - Hardware SPI - MASTER Frame #include #include // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = ON // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) #define _XTAL_FREQ 64000000 // #define MOSI LATCbits.LATC5 // MOSI RC5/SDO #define MISO PORTCbits.RC4 // MISO RC4/SDI #define SS LATBbits.LATB0 // Slave Select / RB0 #define CLK LATCbits.LATC3 // Clock RC3/SCK #define FRAME_SIZE 10 // Frame fixed size unsigned char rx[FRAME_SIZE]; // RX buffer unsigned char tx[FRAME_SIZE]; // TX buffer unsigned char buffer_pointer; // Array index for byte to send or receive void Inizialize_frames(void); // Reset RX and TX buffer void Inizialize_hardware(void); // Configure MSSP and I&O pin void Send_frame(void); // Send first byte of the frame void main(void) { Inizialize_hardware(); // Configure MSSP and I&O pin while (1) { Inizialize_frames(); // Reset RX and TX buffer Send_frame(); // Send first byte of the TX frame // DO SOMETHING... } } void interrupt __high_priority my_isr_high(void) { if (PIR1bits.SSPIF) {// Interrupt from SPI? rx[buffer_pointer] = SSPBUF; // Get data from MSSP and store in RX buffer buffer_pointer++; // Next data if (buffer_pointer < FRAME_SIZE) // Ended? SSPBUF = tx[buffer_pointer]; // Send next byte to SPI else SS = 1; // Disable Slave Select (and stop to send data) PIR1bits.SSPIF = 0; // Clear interrut flag } } void Inizialize_frames(void) { static unsigned char counter = 0; // Clear RX and TX buffer for (int i = 0; i < FRAME_SIZE; i++) { tx[i] = '#'; // Clear TX Buffer rx[i] = '#'; // Clear RX Buffer } // TX Buffer "MASTER x #", x = 0 -> 9 sprintf(tx, "MASTER %i", counter); // Fill TX buffer counter++; // Next counter value (max 9) if (counter >= 10) counter = 0; }; void Send_frame(void) { SS = 0; // Enable Slave Select buffer_pointer = 0; // Point to first byte in TX/RX array SSPBUF = tx[buffer_pointer]; // Send first byte to SPI and return back to main() } void Inizialize_hardware(void) { // Configure SPI pin TRISCbits.RC5 = 0; // Set MOSI pin as output TRISCbits.RC3 = 0; // Set clock pin as output TRISCbits.RC4 = 1; // Set MISO pin as input TRISB=0; // Set Slave Select (PORTB) as output PORTB=0xFF; // Disable all Slave Select SS = 1; // Disable Slave Select CLK = 0; // Clear SPI clock // Configure processor clock to higher speed OSCCONbits.IRCF = 0b111; // Disable prescaler (16 MHz) OSCTUNEbits.PLLEN = 1; // Enable PLL x 4 (64 MHz) // Configure SPI hardware SSPCON1bits.SSPEN = 1; // Synchronous Serial Port Enable bit SSPCON1bits.SSPM = 0b0010; // SPI Master mode, clock = FOSC/64 (1 MHz) SSPSTATbits.CKE = 1; // 1 = Transmit occurs on transition from active to Idle clock state SSPCON1bits.CKP = 0; // Idle state for clock is a low level SSPSTATbits.SMP = 0; // Input data sampled at middle of data output time // Configure interrupt RCONbits.IPEN = 1; // Enable priority levels on interrupts PIE1bits.SSPIE = 1; // Enable interrupt from MSSP IPR1bits.SSPIP = 1; // MSSP Interrupt Priority set to high PIR1bits.SSPIF = 0; // Clear interrupt status to avoid automatic interrupt ad "boot time" INTCONbits.GIE = 1; // Enables all interrupts }