// PIC18 in C - Versione 0.78 - Luglio 2015 // Copyright (c) 2015, Vincenzo Villa // Creative Commons | Attribuzione - Condividi allo stesso modo 4.0 Internazionale (CC BY-SA 4.0) // Creative Commons | Attribution-Share Alike 4.0 Unported // https://www.vincenzov.net/tutorial/PIC18/SPI-interrupt-Timer2.htm // PIC18F25K20 / MPLABX 3.05 / XC8 1.34 // Timer2 and SPI Master: MAX 146 #include // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = ON // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) #define _XTAL_FREQ 64000000 #define MAX146_CONTROL_BYTE 0x8F // 1000 1111 = Channel 0, Unipolar, single ended, external clock (see datasheet) #define MOSI LATCbits.LATC5 // Pin 16 MOSI RC5/SDO #define MISO PORTCbits.RC4 // Pin 15 MISO RC4/SDI #define SS1 LATBbits.LATB1 // Pin 22 ADC_SS RB1 #define CLK LATCbits.LATC3 // Pin 14 SCK RC3/SCK #define SAMPLES 8 // Number of 12 bit data to read from ADC #define TIMER2_VALUE 3 // Count from 0 to 3 unsigned char rx[SAMPLES * 2 + 1]; // RX buffer unsigned char tx[SAMPLES * 2 + 1]; // TX buffer void main(void) { unsigned char buffer_pointer = 0; // Configure SPI pin TRISCbits.RC5 = 0; // Set MOSI pin as output TRISCbits.RC3 = 0; // Set clock pin as output TRISBbits.RB1 = 0; // Set SS1 pin as output TRISCbits.RC4 = 1; // Set MISO pin as input SS1 = 1; // Disable Slave Select (ADC) CLK = 0; // Clear clock // Configure processor clock to high speed OSCCONbits.IRCF = 0b111; // Disable prescaler (16 MHz) OSCTUNEbits.PLLEN = 1; // Enable PLL x 4 (64 MHz) for (int i = 0; i < (SAMPLES * 2 + 1); i++) tx[i] = 0; tx[0] = MAX146_CONTROL_BYTE | 0x00; tx[2] = MAX146_CONTROL_BYTE | 0x40; tx[4] = MAX146_CONTROL_BYTE | 0x10; tx[6] = MAX146_CONTROL_BYTE | 0x50; tx[8] = MAX146_CONTROL_BYTE | 0x20; tx[10] = MAX146_CONTROL_BYTE | 0x60; tx[12] = MAX146_CONTROL_BYTE | 0x30; tx[14] = MAX146_CONTROL_BYTE | 0x70; // Configure SPI hardware SSPCON1bits.SSPEN = 1; // Synchronous Serial Port Enable bit SSPCON1bits.SSPM = 0b0011; // SPI Master mode, clock = TMR2 output/2 (2 MHz)) SSPSTATbits.CKE = 1; // 1 = Transmit occurs on transition from active to Idle clock state SSPCON1bits.CKP = 0; // Idle state for clock is a low level SSPSTATbits.SMP = 0; // Input data sampled at middle of data output time // Configure Timer2 T2CONbits.T2OUTPS = 0; // 1:1 Postscale T2CONbits.T2CKPS = 0; // 1:1 Prescaler PR2 = TIMER2_VALUE; // Timer2 Period Register (64 MHz / 4 / 4 -> 4 MHz) T2CONbits.TMR2ON = 1; // Timer2 is on while (1) { SS1 = 0; // Enable Slave Select (ADC) for (buffer_pointer = 0; buffer_pointer <= (SAMPLES * 2); buffer_pointer++) { SSPBUF = tx[buffer_pointer]; // Write data from TX buffer while (!SSPSTATbits.BF); // SSPBUF is empty? rx[buffer_pointer] = SSPBUF; // Get data from SPI and store in RX buffer } SS1 = 1; // Disable Slave Select (ADC) __delay_ms(1); } }