// PIC18 in C - Versione 0.79 - Luglio 2015
// Copyright (c) 2015, Vincenzo Villa
// Creative Commons | Attribuzione - Condividi allo stesso modo 4.0 Internazionale (CC BY-SA 4.0)
// Creative Commons | Attribution-Share Alike 4.0 Unported
// https://www.vincenzov.net/tutorial/PIC18/SPI.htm

// PIC18F25K20 - Hardware SPI - Esercizio 3
// MPLABX 3.05 - XC8 1.34

#include <xc.h>

// CONFIG1H
#pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = ON        // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)

// CONFIG2L
#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 18        // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal)

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = ON      // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF        // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected)
#pragma config CP1 = OFF        // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected)
#pragma config CP2 = OFF        // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected)
#pragma config CP3 = OFF        // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

#define _XTAL_FREQ 64000000 

#define MOSI LATCbits.LATC5 // Pin 16 MOSI RC5/SDO
#define MISO PORTCbits.RC4 // Pin 15 MISO RC4/SDI
#define SS0  LATBbits.LATB0 // Pin 21 DAC_SS RB0
#define CLK  LATCbits.LATC3 // Pin 14 SCK RC3/SCK

unsigned char SPI_Master_write_read_byte_MSSP(unsigned char dato);

void main(void) {

    unsigned char byte_to_send = 0, byte_recived;

    OSCCONbits.IRCF = 0b111;
    OSCTUNEbits.PLLEN = 1;

    TRISCbits.RC5 = 0; 
    TRISCbits.RC3 = 0; 
    TRISBbits.RB0 = 0;
    TRISCbits.RC4 = 1;

    TRISCbits.RC0 = 0;

    SS0 = 1; 
    CLK = 0;

    SSPCON1bits.SSPEN = 1;
    SSPCON1bits.SSPM = 0b0010;
    SSPSTATbits.CKE = 1;
    SSPCON1bits.CKP = 0;
    SSPSTATbits.SMP = 0;

    while (1) {
        byte_to_send++;

        SS0 = 0;

        byte_recived = SPI_Master_write_read_byte_MSSP(byte_to_send); 

        SS0 = 1;
        byte_recived++;
        if (byte_recived != byte_to_send)
            LATCbits.LATC0 = 1; 
        else
            LATCbits.LATC0 = 0;

        __delay_us(5);
    }
}

unsigned char SPI_Master_write_read_byte_MSSP(unsigned char dato) {
    SSPBUF = dato; 
    while (!SSPSTATbits.BF); 
    return SSPBUF;
}