// PIC18 in C - Versione 0.72 - Luglio 2015 // Copyright (c) 2015, Vincenzo Villa // Creative Commons | Attribuzione - Condividi allo stesso modo 4.0 Internazionale (CC BY-SA 4.0) // Creative Commons | Attribution-Share Alike 3.0 Unported //https://www.vincenzov.net/tutorial/PIC18/timer1.htm // MPLAB X 3.05 - XC8 1.34 - PIC18F25K20 // PIC18F25K20 Configuration Bit Settings #include // CONFIG1H #pragma config FOSC = INTIO67 // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = ON // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 18 // Brown Out Reset Voltage bits (VBOR set to 1.8 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config HFOFST = ON // HFINTOSC Fast Start-up (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection Block 0 (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection Block 1 (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection Block 2 (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection Block 3 (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks) #define TIMER1_VALUE 49999 // T1 count from 0 to 49999 (50000 count) void main(void) { // Configure GPIO TRISC = 0x00; // Set PORTC as output // Configure Timer1 T1CONbits.RD16 = 1; // Enables register read/write of TImer1 in one 16-bit operation T1CONbits.T1RUN = 0; // Main system clock is derived from another source T1CONbits.T1CKPS = 0; // 1:1 Prescale value T1CONbits.T1OSCEN = 0; // Timer1 oscillator is shut off T1CONbits.TMR1CS = 0; // Internal clock (F OSC /4) T1CONbits.TMR1ON = 0; // Stops Timer1 // Configure ECCP1 CCP1CONbits.CCP1M = 0b1011; //Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit) T3CONbits.T3CCP1 = 0b01; // Timer1 is the capture/compare clock source for CCP1 IPR1bits.CCP1IP = 1; // CCP1 Interrupt Priority set to highc PIE1bits.CCP1IE = 1; // Enables the CCP1 interrupt CCPR1H = TIMER1_VALUE >> 8; CCPR1L = TIMER1_VALUE & 0xFF; // Configure interruppt RCONbits.IPEN = 1; // Enable priority levels on interrupts T1CONbits.TMR1ON = 1; //Enables Timer1 INTCONbits.GIEH = 1; // Enables all interrupts while (1); } void interrupt __high_priority my_isr_high(void) { if (PIR1bits.CCP1IF == 1) // Interrupt from ECCP ? { LATCbits.LC2 = ~LATCbits.LC2; // Change LED status PIR1bits.CCP1IF = 0; // Clear interrupt status } }